Semiconductor devices, cmos image sensors, and methods of manufacturing same

ABSTRACT

A semiconductor device includes: a trench device isolating region formed in a substrate to define a photodiode active region; a channel stop impurity region formed in the substrate contacting the device isolating region, wherein the channel stop impurity region surrounds a bottom and a sidewall of the device isolating region; and a photodiode formed within the photodiode active region.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This is a divisional application of co-pending U.S. application Ser. No.11/517,238 filed Sep. 7, 2006, which claims foreign priority under 35U.S.C. § 119 to Korean Patent Application No. 10-2005-0124112 filed Dec.15, 2005, which are hereby incorporated by reference for all purposes asif fully set forth herein.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to semiconductor devices, image sensors,and methods of manufacturing the same and, more particularly, tosemiconductor devices having a trench, CMOS image sensors having atrench, and methods of manufacturing semiconductor devices and the CMOSimage sensors.

2. Discussion of the Related Art

Image sensors are semiconductor devices that convert optical images intoelectrical signals. Image sensors can be classified into Charge CoupledDevice (CCD) image sensors and CMOS Image Sensors. A CMOS image sensorincludes a photodiode that receives optical signals and a MOS transistorthat controls the optical signals within a unit pixel. The CCD imagesensor has a complicated driving system and a complicated manufacturingprocess. Signal processing circuits are difficult to fabricate in oneCCD chip. In contrast, the CMOS image sensor can be manufactured bystandard CMOS techniques, and can be integrated into a single circuittogether with other signal processing circuits.

CMOS image sensor fabrication includes forming a device isolating layeron a silicon substrate to define the photodiode active regions and MOStransistor active regions. A CMOS image sensor may exhibit crystallinedefects such as dangling bond at an interfacial surface between thedevice isolating layer and the substrate of the photodiode activeregion. For example, when the device isolating layer has a ShallowTrench Isolation (STI) structure, such as a trench formed by etching thesubstrate and filled with an insulating layer, crystalline defects mayoccur when etching the substrate. The crystalline defects, which act astraps capturing electrons, may become defect or noise components of eachpixel, increasing the dark current, i.e., the current that continues toflow in the photodiode when there is no incident light. Thus thecrystalline defects of the device isolation region can degrade theimaging characteristics of the CMOS image sensor.

Forming an impurity region within a lower portion of the trench usingion implantation is difficult. Because the ion beam used for ionimplantation has forward directivity, the impurity region is mostlyformed under the trench without surrounding the sides of the trench. Theion beam or substrate may be tilted during the implantation process sothat the impurity region is formed on the sides of the trench, but withno impurity region formed under the trench. A crystalline defectoccurring in the interfacial surface of a trench that is not surroundedby an impurity region may generate the dark current. As semiconductordevices become ever more highly integrated, the trenches are furtherdeepened and narrowed. In such case, it becomes more difficult to formthe impurity region by ion implantation to surround the trench. As aresult, the dark current may be increased.

Moreover, because ion implantation is performed under a relatively highenergy condition, the impurity region is generally thickly formed. Thisis apt to shrink the depletion region of the photodiode formed adjacentto the trench, which may decrease the saturation current of thephotodiode.

SUMMARY OF THE INVENTION

According to an exemplary embodiment of the present invention, a methodof manufacturing a semiconductor device includes: forming a trench in asubstrate to define a photodiode active region; doping an impurity intoa bottom and a sidewall of the trench to form a channel stop impurityregion, wherein the channel stop impurity region surrounds the bottomand the sidewall of the trench; forming a trench device isolating regionby forming a gap-filling material layer into the impurity-doped trench;and forming a photodiode in the photodiode active region. The dopingstep may be performed by plasma doping.

The plasma doping may be performed using at least one of a dopant gas ora dilution gas.

The trench may be comprised of a deep trench configuration. Thesubstrate may include a base substrate and an epitaxial layer formed onthe base substrate, and the trench may be formed to penetrate throughthe epitaxial layer.

According to an exemplary embodiment of the present invention, a methodof manufacturing an image sensor includes: forming a circuit trenchwithin a peripheral circuit region to define a circuit active region,and forming a pixel trench within the pixel region to define aphotodiode active region; doping an impurity into a bottom and asidewall of the pixel trench to form a channel stop impurity region,wherein the channel stop impurity region surrounds the bottom and thesidewall of the pixel trench; forming a gap-filling material layer intothe circuit trench to form a circuit trench device isolating region;forming a gap-filling material layer into the impurity-doped pixeltrench to form a pixel trench device isolating region; and forming aphotodiode within the photodiode active region.

The depth of the pixel trench may be deeper than depth of the circuittrench. The substrate may include a base substrate and an epitaxiallayer formed on the base substrate, the circuit trench may be formedwithin the epitaxial layer, and the pixel trench may be formed topenetrate through the epitaxial layer.

According to an exemplary embodiment of the present invention, asemiconductor device includes: a trench device isolating region formedin a substrate to define a photodiode active region; a channel stopimpurity region formed in the substrate contacting the device isolatingregion, wherein the channel stop impurity region surrounds a bottom anda sidewall of the device isolating region; and a photodiode formedwithin the photodiode active region.

An impurity density within the channel stop impurity region may becontinuously decreased away from the device isolating region.

The thickness of the channel stop impurity region on the side of thedevice isolating region may have a ratio of 0.5 to 1 with respect to athickness of the channel stop impurity region under the device isolatingregion.

According to an exemplary embodiment of the present invention, an imagesensor includes: a substrate having a pixel region and a peripheralcircuit region; a circuit trench device isolating region formed in theperipheral circuit region to define a circuit active region; a pixeltrench device isolating region formed in the pixel region to define aphotodiode active region; a channel stop impurity region formed in thesubstrate contacting the pixel trench device isolating region, whereinthe channel stop impurity region surrounds a bottom and a sidewall ofthe pixel trench device isolating region; and a photodiode formed in thesubstrate of the photodiode active region.

The depth of the pixel trench device isolating region may be greaterthan the depth of the circuit trench device isolating region. Thesubstrate may include a base substrate and an epitaxial layer formed onthe base substrate, the pixel trench device isolating region may beformed within the epitaxial layer, and the pixel trench device isolatingregion may be formed to penetrate through the epitaxial layer.

The present invention will become readily apparent to those of ordinaryskill in the art when descriptions of exemplary embodiments thereof areread with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram of a unit pixel of a CMOS imagesensor according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view partially illustrating a pixel array unit,according to an exemplary embodiment of the present invention, forembodying the CMOS image sensor illustrated in FIG. 1.

FIGS. 3A through 3F are sectional views illustrating a method ofmanufacturing the CMOS image sensor according to an exemplary embodimentof the present invention, taken along a line I-I of FIG. 2.

FIG. 4 is a diagrammatic view illustrating a computer processor systemprovided with the CMOS image sensor according to an exemplary embodimentof the present invention.

FIG. 5 is a graph showing a boron density in relation to the sidewalldepth of the specimens resulting from Experiments 3 and 4 and Comparison2.

FIG. 6 is a photograph showing a trench device isolating region byExperiment 2.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, exemplary embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings. It willbe understood that when an element such as a layer, film, region, orsubstrate is referred to as being “on” another element, it can bedirectly on the other element, or intervening elements may also bepresent. Like reference numerals refer to similar or identical elementsthroughout the description of the figures.

FIG. 1 is an equivalent circuit diagram of a unit pixel of a CMOS imagesensor according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a unit pixel PX includes a first photodiode 140, asecond photodiode 150, a first transfer transistor 120, a secondtransfer transistor 130, a reset transistor 160, a drive transistor 170,and a select transistor 180.

The first and second photodiodes 140 and 150 are respectively connectedto sources of the first and second transfer transistors 120 and 130.Drains of the transfer transistors 120 and 130 commonly share a floatingdiffusion region FD that is a floating node. The reset transistor 160,the select transistor 180, and the drive transistor 170 are seriallyconnected to the floating node FD. The floating node FD is alsoconnected to a gate of the drive transistor 170. A power source Vdd isconnected to a node between the reset transistor 160 and the selecttransistor 180.

Hereafter, driving a unit pixel PX, according to an exemplary embodimentof the present invention, will be described with reference to FIG. 1.First, when a reset signal R_(x) is supplied to a gate of the resettransistor 160, the reset transistor 160 is turned on. The electricalpotential of the floating node FD is reset to a power source voltage.Then, the reset transistor 160 is turned off. The incident light on thephotodiodes 140 and 150 causes electron-hole pairs to be generated inproportion to the incident light. The generated signal charges aretrapped to the photodiodes 140 and 150 by gate barriers of the transfertransistors 120 and 130.

When a transfer signal T_(x1) is supplied to a gate of either one of thetransfer transistors 120 or 130, it is turned on. For example, if thetransfer signal T_(x1) is supplied to the first transfer transistor 120,the first transfer transistor 120 is turned on. In such case, the signalcharges trapped to the first photodiode 140 are transferred to thefloating node FD to change the potential of the floating node FD. Thegate bias of the drive transistor 170 is changed, and thus currentdrivability of the drive transistor 170 is determined. At this time, aselect signal SEL is supplied to a gate of the select transistor 180,and the select transistor 180 is turned on. As the result, a currentcorresponding to the potential of the floating node FD flows through thedrive transistor 170, which is supplied as an output voltage Vout. Here,T_(x2) denotes a transfer signal supplied to a gate of the secondtransfer transistor 130.

As described above, the unit pixel includes at least two photodiodes,and the transistors are commonly shared to provide the signals from thephotodiodes, and the unit pixel area is decreased, allowing for bothhigher integration and increased fill factor. It is to be understoodthat the unit pixel may have a single photodiode or at least threephotodiodes, and arrangement and number of the transistors may bemodified appropriately.

FIG. 2 is a plan view partially illustrating of a pixel array unit,according to an exemplary embodiment of the present invention, forembodying the CMOS image sensor illustrated in FIG. 1.

Referring to FIG. 2, the pixel array unit includes unit pixels PXarranged in rows and columns. The unit pixel PX includes a first activeregion 110 and a second active region 115 defied by forming a trenchdevice isolating region in a predetermined region of a substrate. Thefirst active region 110 includes first and second photodiode activeregions 110_1 and 110 _(—)2 spaced apart from each other, and a transfertransistor active region 110_3 extending from the first and secondphotodiode active regions 110_1 and 110_2 to connect the first andsecond photodiode active regions 110_1 and 110_2. A reset transistoractive region 110_4 extends from the transfer transistor active region110_3. First and second photodiodes 140 and 150 are formed into thefirst and second photodiode active regions 110_1 and 110_2.

A first transfer gate electrode 123, the second transfer gate electrode133, a reset gate electrode 163, a select gate electrode 183, and adrive gate electrode 173 are arranged on the first and second activeregions 110 and 115. The first and second transfer gate electrodes 123and 133 traverse over the transfer transistor active region 110_3 in amanner of being respectively adjacent to the first and second photodiodeactive regions 110_1 and 110_2. A floating diffusion region FD is formedin the transfer transistor active region 110_3 exposed between the firstand second transfer gate electrodes 123 and 133. The reset gateelectrode 163 traverses over the reset transistor active region 110_4,and is adjacent to the floating diffusion region FD. Also, the selectgate electrode 183 and the drive gate electrode 173 traverse over thesecond active region 115.

Interconnects (not shown) are disposed on the gate electrodes 123, 133,163, 173 and 183. For example, an interconnect allows an active regionopposite to the floating diffusion region FD out of the reset transistoractive region 110_4 adjacent to the reset gate electrode 163 to beelectrically connected to the second active region 115 exposed to oneside of the select gate electrode 183, and is connected to the powersource (Vdd of FIG. 1). Another interconnect allows the floatingdiffusion region FD to be electrically connected to the drive gateelectrode 173.

On the other hand, intervals Wa and Wb between the photodiodes 140 and150 may be reduced to decrease the area of the unit pixel PX andincrease the fill factor. To prevent crosstalk from occurring betweenthe photodiodes 140 and 150, the trench device isolating region betweenthe first and second photodiode active regions 110_1 and 110_2 may befurther deepened.

FIGS. 3A through 3F are sectional views illustrating a method ofmanufacturing the CMOS image sensor according to an exemplary embodimentof the present invention, which illustrate a pixel region and aperipheral circuit region taken along a line I-I of FIG. 2. Theperipheral circuit region is placed in a periphery of the pixel arrayunit illustrated in FIG. 2, and a driving circuit to drive the pixelarray unit is disposed therein.

Referring to FIG. 3A, a substrate 100′ having a pixel region and aperipheral circuit region is prepared. The substrate 100′ has a basesubstrate 100, and an epitaxial layer 101 having a first conductivitytype and formed on the base substrate 100. The first conductivity typemay be a P-type.

A pad insulating layer 103 and a hard mask layer 104 are sequentiallystacked on the substrate 100′. The hard mask layer 104 is used as a hardmask, e.g., a silicon nitride layer, when forming a trench that will bedescribed later. The pad insulating layer 103, e.g., a silicon oxidelayer, relieves stress applied to the substrate 100′ when stacking thehard mask layer 104.

A photoresist pattern (not shown) is formed on the hard mask 104. Usingthe photoresist pattern as a mask, the hard mask layer 104 and the padinsulating layer 103 is etched, thereby partially exposing the substrate100′. Then, the photoresist pattern is removed.

The hard mask layer 104 is used as a mask to etch an exposed area of thesubstrate 100′. The trenches 100 a and 100 b are formed in the substrate100′. In an exemplary embodiment of the present invention, the trenches100 a and 100 b are formed in the epitaxial layer 101 and define theactive regions. For example, the pixel trench 100 a, formed in thesubstrate 100′ of the pixel region, defines a pixel active region. Thecircuit trench 100 b, defines a circuit active region formed in thesubstrate 100′ of the peripheral circuit region. The pixel active regionincludes the first and second photodiode active regions 110_1 and 110_2of FIG. 2) and the transfer transistor active region (110_3 of FIG. 2).

Referring to FIG. 3B, a buffer insulating layer 105 is stacked on thesubstrate 100′ where the trenches 100 a and 100 b are formed. The bufferinsulating layer 105 is formed on the hard mask layer 104 by filling upthe trenches 100 a and 100 b. A photoresist pattern 109 is formed on thebuffer insulating layer 105. The photoresist pattern 109 covers anentire surface of the peripheral circuit region, but, in the pixelregion, is aligned to the hard mask layer 104 to expose the bufferinsulating layer 105 on an upper surface of the pixel trench 100 a.

Using the photoresist pattern 109 as a mask, the exposed bufferinsulating layer 105 is etched. Therefore, the buffer insulating layer105 within the pixel trench 100 a is thoroughly etched, and a bottom ofthe pixel trench 100 a is exposed. Then, the bottom of the exposed pixeltrench 100 a is etched to form a deep pixel trench 100 a′ as illustratedin FIG. 3C.

While the deep pixel trench 100 a′ is formed, the photoresist pattern109 may be etched, and an upper surface of the buffer insulating layer105 may be partially etched. The buffer insulating layer 105 acts as anetch buffer layer that does not expose the hard mask layer 104 whileforming the deep pixel trench 100 a′ as described above.

Referring to FIG. 3C, the depth of deep pixel trench 100 a′ is greaterthan that of the circuit trench 100 b. The photodiode active regions(110_1 and 110_2 of FIG. 2) are sufficiently separated from each otherto prevent the crosstalk apt to occurring between the photodiodes thatwill be formed in a subsequent process. According to an exemplaryembodiment of the present invention, deep pixel trench 100 a′ has adepth of about 1 μm to about 4 μm, and may prevent crosstalk. Thecircuit trench 100 b may be a shallow trench having a depth of about 0.4μm or less. However, it is to be understood that the pixel trench may beformed as a shallow trench of 0.4 μm or less.

Both the deep pixel trench 100 a′ and the circuit trench 100 b may beformed within the epitaxial layer 101. It is to be understood that thecircuit trench 100 b may be formed within the epitaxial layer 101 andthe deep pixel trench 100 a′ may penetrate through the epitaxial layer101.

Thereafter, an impurity is doped into the bottom and the sidewall of thepixel trench 100 a′ to form a channel stop impurity region 106 thatsurrounds the bottom and the sidewall of the pixel trench 100 a′. Whenthe channel stop impurity region 106 completely surrounds the bottom andthe sidewall of the pixel trench 100 a′, the exposure of an interfacialsurface of the pixel trench 100 a′ is prevented. In an exemplaryembodiment of the present invention, the channel stop impurity region106 conformally surrounds the bottom and the sidewall of the pixeltrench 100 a′, and the dark current and noise caused by an interfacialsurface defect of the pixel trench 100 a′ can be decreased.

The impurity doping may be a plasma doping process. For example, thesubstrate 100 having the pixel trench 100 a′ is placed within a plasmadoping chamber (not shown), and dopant gas as a source gas is inducedinto the chamber. Then, the dopant gas is used to generate plasma, and avoltage is supplied to the substrate 100 to dope ions of the plasma intothe substrate 100, e.g., the inside of the pixel trench 100 a′. In anexemplary embodiment of the present invention, the plasma forms thechannel stop impurity region 106 that surrounds the bottom and sidewallof the pixel trench 100 a′. For example, when the pixel trench 100 a′ isformed as a deep trench configuration as described above, plasma dopingmay effectively form the channel stop impurity region 106 that surroundsthe bottom and the sidewall of the deep trench. When plasma doping isused, the impurity is distributed by concentrating on a portion incontact with the pixel trench 100 a′, and a density of the impurity iscontinuously decreased away from the pixel trench 100 a′. The channelstop impurity region 106 may be thinly formed and a depletion region ofthe photodiode that will be formed later is not reduced, and thedecrease of the saturation current may be prevented.

The dopant gas may comprise, for example, BF₃, B₂H₆, BCl₃ or anycombinations thereof. Boron may be doped into the channel stop impurityregion 106. The source gas may include a dilution gas together with thedopant gas. The dilution gas may comprise, for example, H₂, N₂, O₂, F₂,He, Ar, Xe, or any combinations thereof. The dilution gas may be evenlydispersed in a density of plasma, distributing the channel stop impurityregion 106 throughout the bottom and the sidewall of the pixel trench100 a′. In exemplary embodiments of the present invention, the channelstop impurity region 106 surrounds the bottom and the sidewall of thedeep trench. For example, the thickness of the channel stop impurityregion 106 on the side of the pixel trench 100 a′ may have a ratio of0.5 to 1 with respect to the thickness of the channel stop impurityregion 106 under the pixel trench 100 a′.

Before doping the impurity, an oxide layer 108 may be formed within thepixel trench 100 a′. The oxide layer 108 may block an inflow of amaterial besides boron when performing plasma doping. The oxide layer108 may be a thermal oxide layer. When forming the thermal oxide layer,damages such as a lattice defect occurring within the trench 100 a′ maybe relieved. For example, plasma doping may be performed with an energyin a range of about 1 kV to 7 kV, and may prevent the dark current andprevent the decrease of the saturation current.

In an exemplary embodiment of the present invention, plasma doping isperformed with a dose in a range of about 0.1E13 atoms/cm² to about1.0E18 atoms/cm².

Referring to FIG. 3D, a gap-filling material layer 107 is formed withinthe impurity-doped pixel trench 100 a′. The gap-filling material layer107 may comprise an insulating layer. The gap-filling material layer 107is formed on an upper surface of the buffer insulating layer 105. Thegap-filling material layer 107 may comprise an insulating material, suchas for example, a High Density Plasma-Chemical Vapor Deposition(HDP-CVD) oxide with an excellent gap-fill property or Undoped SilicaGlass (USG). Chemical mechanical Polishing (CMP) is performed on thesubstrate 100′ having the gap-filling material layer 107 thereon untilthe hard mask layer 104 is exposed, thereby planarizing the gap-fillingmaterial layer 107 and the buffer insulating layer 105. Thereafter, thehard mask layer 104 and the pad insulating layer 103 are removed toexpose the active regions.

As illustrated in FIG. 3E, the pixel trench device isolating region 100a″, the gap-filling material layer 107, the circuit trench deviceisolating region 100 b′, and the buffer insulating layer 105 are formed.

An impurity having a second conductivity type is implanted within thesubstrate 100′ of the peripheral circuit region, thereby forming a well102 having the second conductivity type. For example, the secondconductivity type may be an N-type. Thereafter, a gate insulating layer119 is formed on the substrate 100′, and a gate conductive layer isformed on the gate insulating layer 119. The gate conductive layer maybe a doped polysilicon layer. The gate conductive layer is patterned toform a first transfer gate electrode 123 and a second transfer gateelectrode 133 on the transfer transistor active region (110_3 of FIG.2), and a circuit gate electrode 193 on the circuit active region. Thegate insulating layer 119 may also be patterned. The first and secondtransfer gate electrodes 123 and 133 are formed adjacently to the firstand second photodiode active regions (110_1 and 110_2 of FIG. 2),respectively.

A first photoresist pattern that exposes the transfer transistor activeregion 110_3 is formed. Then, using the first photoresist pattern andthe first and second transfer gate electrodes 123 and 133 as masks, theimpurity having the second conductivity type is implanted to form afloating diffusion region FD.

Thereafter, the first photoresist pattern is removed, and a secondphotoresist pattern for exposing the circuit active region is formed.Using the second photoresist pattern and the circuit gate electrode 193as masks, the impurity having the first conductivity type is implantedto form source/drain regions 195.

A third photoresist pattern (not shown) to expose the photodiode activeregions (110_1 and 110_2 of FIG. 2) is formed. Using the thirdphotoresist pattern as a mask, the impurity having the secondconductivity type is implanted into the first and second photodiodeactive regions (110_1 and 110_2 of FIG. 2) at a high energy, formingfirst and second lower impurity regions 147 and 157. Then, the thirdphotoresist pattern is removed.

Referring to FIG. 3F, a spacer insulating layer is stacked on thesubstrate 100′. The spacer insulating layer is anisotropically etched toform spacers 129 along sidewalls of the gate electrodes 123, 133, and193. A fourth photoresist pattern to expose the photodiode activeregions (110_1 and 110_2 of FIG. 2) is formed on the substrate 100′where the spacers 129 are formed. Using the fourth photoresist patternand the spacers 129 as masks, the impurity having the first conductivitytype is implanted at a low energy to form first and second upperimpurity regions 145 and 155. The first and second upper impurityregions 145 and 155 are formed within the first and second lowerimpurity regions 147 and 157, respectively. The first upper impurityregion 145 and the first lower impurity region 147 comprise the firstphotodiode 140. The second upper impurity region 155 and the secondlower impurity region 157 comprise the second photodiode 150.

The first and second upper impurity regions 145 and 155 may be formedusing plasma doping. According to an exemplary embodiment of the presentinvention, the impurity density within the first and second upperimpurity regions 145 and 155 are concentrated on the surface of thesubstrate 100′, so that the first and second upper impurity regions 145and 155 may be thinly formed, and the thickness of a depletion region isincreased when the photodiodes 140 and 150 are operated, improvingphotosensitivity of the photodiodes 140 and 150.

FIG. 4 is a diagrammatic view illustrating a computer processor systemprovided with the CMOS image sensor according to an exemplary embodimentof the present invention.

Referring to FIG. 4, a computer processor system 300 includes a CentralProcessor Unit (CPU) 320, a floppy disc drive 330, a CDROM drive 340, aCMOS image sensor 310, an I/O unit 360, and a RAM 350. The CMOS imagesensor 310 may be embodied as described above with reference to FIGS. 1,2, and 3A through 3F. The CPU 320, the CMOS image sensor 310, and theRAM 350 may be equipped within a System on Chip (SoC).

The CPU 320, the floppy disc drive 330, the CDROM drive 340, the CMOSimage sensor 310, the I/O unit 360, and the RAM 350 may be mutuallycommunicated via a bus 370. Hereinafter, examples of experiments arepresented to assist in understanding of exemplary embodiments of thepresent invention.

Dark Current and Random Noise Characteristics of CMOS Image Sensors

<Experiment 1>

An epitaxial layer is formed on a substrate, and a mask patterncomprising a silicon oxide layer and a silicon nitride layer is formedon the epitaxial layer. Using the mask pattern as a mask, the epitaxiallayer is etched to a depth of about 0.3 μm to form a trench, defining aphotodiode active region. Boron is doped into a bottom and a sidewall ofthe trench using plasma doping, forming a channel stop impurity region.When performing a plasma doping process, BF₃ is used as a source gas.The doping energy is 3 kV and the dose of BF₃ is 1.0E15 atoms/cm². AnHDP-CVD oxide layer is buried into the trench doped with boron, and theHDP-CVD oxide layer is planarized by CMP. Thereafter, the siliconnitride layer and the silicon oxide layer are removed to form a trenchdevice isolating region. Phosphorus ions are implanted into thephotodiode active region to form a lower impurity region, and boron isimplanted to the photodiode active region to form an upper impurityregion.

<Experiment 2>

A specimen is manufactured in the same manner as that of Experiment 1,except that BF₃ and N₂ are used as source gases when performing plasmadoping, wherein the fluid quantity ratios of BF₃ and N₂ are 20% and 80%,respectively.

<Comparison 1>

When doping boron into the trench, plasma doping is not used. Instead,boron is implanted under process conditions of 30 kV and 1.2E13atoms/cm², and again implanted under process conditions of 10 kV and6.0E12 atoms/cm². All other process conditions and steps are the same asthose of Experiment 1.

The measured dark current and random noise characteristics of thespecimens according to Experiment 1, Experiment 2, and Comparison 1 arelisted in Table 1.

TABLE 1 Boron Doping conditions within Trench Dark Current Noise PlasmaDoping Ion Implantation (mV/sec) (LSB) Experiment 1 BF₃, 3 kV, — 6 3.971.0E15 atoms/cm² Experiment 2 BF₃, 3 kV, — 7.5 3.65 1.0E15 atoms/cm²(20% BF₃, 80% N₂) Comparison 1 — B, 30 kV, 14 4.65 1.2E13 atoms/cm² B,10 kV 6.0E12 atoms/cm²

Referring to Table 1, when boron is doped within the trench, thespecimens according to Experiments 1 and 2 that use plasma doping havedecreased dark current and lower noise than those of the specimen ofComparison 1. Experiment 2, in which N₂ is added as a dilution gas,exhibits a noise value less than that of Experiment 1. When an impurityis doped into the bottom and the sidewalls of the trench, the darkcurrent characteristic and the random noise characteristic can beimproved when using plasma doping.

When the inside of the trench is doped using plasma doping, a channelstop region completely surrounds the bottom and sidewall of the trench.Such a channel stop impurity region prevents charges which are generatedfrom an interfacial surface of the trench involving a crystalline defectfrom reaching a photodiode, and the dark current and the noise may bedecreased.

Doping Profile of the Bottom and Sidewall of the Trench

FIG. 6 is a photograph taking the trench device isolating region by theExperiment 2.

Referring to FIG. 6, the thicknesses W₂ and W₃ of the channel stopimpurity region 106 in both sides of the trench 100 a are 65.74 nm and61.07 nm, respectively. The thickness W₁ of the channel stop impurityregion 106 under the trench 100 a is 72.37 nm. Therefore, the thicknessof the channel stop impurity region 106 in the side of the trench 100 ahas a ratio of 0.86 or 0.91 with respect to the channel stop impurityregion 106 under the trench 100 a.

When BF₃ is solely used as the source gas without using the dilution gas(Experiment 1), the thickness of the channel stop impurity region on theside of the trench has a ratio of roughly 0.5 with respect to that underthe trench.

When the channel stop impurity region is formed using plasma doping, thethickness of the channel stop impurity region on the side of the trenchhas a ratio of 0.5 to 1 with respect to that under the trench. When thechannel stop impurity region is formed using plasma doping, the channelstop impurity region conformally encloses the sidewall of the trench.When the dilution gas is used during plasma doping, the conformality canbe improved.

Doping Profile within the Substrate

A substrate having an epitaxial layer is prepared, and boron is dopedinto the substrate using plasma doping, thereby forming an impurityregion. When performing plasma doping, BF₃ and N₂ are used as sourcegases. Also, a fluid quantity ratio of BF₃ and N₂ are 20% and 80%,respectively. A doping energy is 3 kV and a dose of BF₃ is 1.0E15atoms/cm².

<Experiment 4>

A specimen is manufactured in the same manner as that of the Experiment3, except that the doping energy during plasma doping is 1 kV.

<Comparison 2>

A substrate having an epitaxial layer is prepared. Boron is ionimplanted under process conditions of 30 kV and 1.2E13 atoms/cm², andagain implanted under conditions of 10 kB and 6.0E12 atoms/cm², therebyforming a boron-doped impurity region within the substrate.

The process conditions for doping boron into the specimens according toExperiment 3, Experiment 4, and Comparison 2 are listed in Table 2.

TABLE 2 Boron Doping Conditions within Trench Plasma Doping IonImplantation Experiment 3 BF₃, 3 kV, — 1.0E15 atoms/cm² (20% BF₃, 80%N₂) Experiment 4 BF3, 1 kV, — 1.0E15 atoms/cm² (20% BF₃, 80% N₂)Comparison 2 — B, 30 kV, 1.2E13 atoms/cm² B, 10 kV, 6.0E12 atoms/cm²

FIG. 5 is a graph showing the boron density in relation to the sidewalldepth of the specimens resulting from Experiments 3 and 4 and Comparison2. In FIG. 5, a, b and c respectively denote the specimens ofExperiments 3 and 4 and Comparison 2.

Referring to FIG. 5, the specimens a and b of Experiments 3 and 4 have aconsiderable quantity of the impurities on the surface of the substrate,and the density of the impurity is continuously decreased with depthfrom the surface of the substrate. The specimen c of Comparison 2 has animpurity density that decreased until reaching a depth of 0.01 μm fromthe surface of the substrate.

In view of these experiments, the impurity region formed using ionimplantation is thicker than that formed using plasma doping. Althoughion implantation performed by tilting an ion beam is used to form achannel stop impurity region into the side of the trench, the impurityregion is thickly formed and decreases the depletion region of thephotodiode that is adjacent to the side of the trench. In contrast, thechannel stop impurity region formed by plasma doping does not affect thedepletion region of the photodiode. Therefore, when the channel stopimpurity region is formed using plasma doping, the decrease of thesaturation current can be prevented.

According to an exemplary embodiment of the present invention animpurity is doped to a bottom and a sidewall of a trench to form achannel stop impurity region that completely surrounds the bottom andthe sidewall of the trench, and dark current and noise may be decreased.In an exemplary embodiment of the present invention, the impurity dopingis performed by plasma doping to thinly form the entire channel stopimpurity region, preventing the decrease of the saturation current of aCMOS image sensor.

Although the exemplary embodiments of the present invention have beendescribed in detail with reference to the accompanying drawings for thepurpose of illustration, it is to be understood that the inventiveprocesses and devices should not be construed as limited thereby. Itwill be readily apparent to those of reasonable skill in the art thatvarious modifications to the foregoing exemplary embodiments can be madetherein without departing from the scope of the invention as defined bythe appended claims, with equivalents of the claims to be includedtherein.

1. A semiconductor device comprising: a trench device isolating regionformed in a substrate to define a photodiode active region; a channelstop impurity region formed in the substrate contacting the deviceisolating region, wherein the channel stop impurity region surrounds abottom and a sidewall of the device isolating region; and a photodiodeformed within the photodiode active region.
 2. The semiconductor deviceof claim 1, wherein an impurity density within the channel stop impurityregion is continuously decreased away from the device isolating region.3. The semiconductor device of claim 1, wherein a thickness of thechannel stop impurity region on the side of the device isolating regionhas a ratio of 0.5 to 1 with respect to a thickness of the channel stopimpurity region under the device isolating region.
 4. The semiconductordevice of claim 1, wherein the trench is comprised of a deep trenchconfiguration.
 5. The semiconductor device of claim 4, wherein the depthof the trench is about 1 μm to about 4 μm.
 6. The semiconductor deviceof claim 1, wherein the substrate comprises a base substrate and anepitaxial layer formed on the base substrate, and wherein the trenchpenetrates through the epitaxial layer.
 7. The semiconductor device ofclaim 1, wherein the semiconductor device comprises an image sensor. 8.An image sensor comprising: a substrate having a pixel region and aperipheral circuit region; a circuit trench device isolating regionformed in the peripheral circuit region to define a circuit activeregion; a pixel trench device isolating region formed in the pixelregion to define a photodiode active region; a channel stop impurityregion formed in the substrate contacting the pixel trench deviceisolating region, wherein the channel stop impurity region surrounds abottom and a sidewall of the pixel trench device isolating region; and aphotodiode formed in the photodiode active region.
 9. The image sensorof claim 8, wherein the depth of the pixel trench device isolatingregion is greater than the depth of the circuit trench device isolatingregion.
 10. The image sensor of claim 9, wherein the depth of the pixeltrench device isolating region is about 1 μm to about 4 μm.
 11. Theimage sensor of claim 8, wherein an impurity density within the channelstop impurity region is continuously decreased away from the pixeltrench device isolating region.
 12. The image sensor of claim 8, whereina thickness of the channel stop impurity region on the side of the pixeltrench device isolating region has a ratio of 0.5 to 1 with respect to athickness of the channel stop impurity region under the device isolatingregion.
 13. The image sensor of claim 8, wherein the substrate comprisesa base substrate and an epitaxial layer stacked on the base substrate,wherein the pixel trench device isolating region is formed within theepitaxial layer, and wherein the pixel trench device isolating regionpenetrates through the epitaxial layer.